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IP Highspeed Electrical Compliance Lead

2.00 to 5.00 Years   Bangalore   21 Feb, 2022
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryTelecom / ISP
Functional AreaService / Installation / Repair
EmploymentTypeFull-time

Job Description

    Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. IP / INTERFACE COMPLIANCE TESTING LEAD ENGINEER THE ROLE: This job opening is for an Electrical interface/IP compliance testing engineer in a team responsible for high-complex platform design & IP validation in AMD s microprocessor designs. With a good mix of experienced designers and recent college graduates from top Engineering institutions across the country, this team offers a very competitive atmosphere with excellent scope to learn and improve. Meticulous execution routine resulting in a solid track record, a strong focus on innovation and a balanced work-life distribution makes this one of the top-class teams in this space across the industry. THE PERSON: Ideal candidate would be the one with not only strong in IP / Interface Electrical compliance testing & validation, but also clear communication and presentation skills along with diligent documentation of work. Passion to go beyond the call of duty and innovate for higher efficiency would be a key differentiator. KEY RESPONSIBILITIES:
    • Complete ownership of all high-speed Ser-des and LSIO interface compliance testing.
    • Complete ownership of debugging signal and power integrity issues of high-speed serial interfaces on platforms.
    • Experience working with the actual product package/board design and analysis and lab correlation/validation of the simulation results.
    • Interface with cross-functional teams like Layout, FW, SI/PI, Mechanical & Thermal.
    PREFERRED EXPERIENCE:
    • Experience in compliance testing for DDRx, PCIe Gen 3.0/4.0/5.0, SATA, HDMI, DP & eDP ports.,
    • Experience in handling all high speed equipment s (Real time scopes, SAMPLING Scopes, JBERT & VNA)
    • Experience in working with PHY & Silicon teams on fine tuning the Tx and Rx settings for better IP / interface electrical compliance.
    • Possess strong fundamentals in 3D/2D EM simulation tools and transmission line theory
    • Expertise in DDRx memory bus compliance validation preferably using Keysight tool chain.
    • Expertise in the compliance testing of serial links including NRZ, multilevel signaling (PAM4), COM, JTOL, Rx sensitivity and SERDES equalization techniques with CTLE, DFE and FFE is required.
    • Hands on experience in De-embedding and embedding of channels for compliance measurements.
    • At the minimum working level knowledge with Cadence Allegro design layout tool, its constraint manager, and schematics.
    • A high-level knowledge about behavioral device modeling including IBIS and IBIS-AMI models as well as passive device modeling techniques with touchstone files.
    • A high-level knowledge about SI and PCB design fundamentals including single ended and differential signals, signal loss, impedance control and crosstalk noise is required.
    • A good grasp of fundamentals circuit and electromagnetics theory including frequency and time domain analysis techniques, transmission line theory, termination techniques, generating and interpreting data-eye diagrams, bathtub curves with NRZ and PAM4 signaling techniques.
    • Significant SI lab experience with TDR and VNA measurements.
    • Maintain standards compliance
    • Anticipate, identify, and solve problems independently
    • Be self-motivated and willing and able to operate with little direct guidance or supervision, work effectively with incomplete or un-defined requirements.
    • Basic platform Board bring-up & testing.
    • Layout review and co-ordination with cross functional teams
    • Interaction with cross functional teams
    ACADEMIC CREDENTIALS:
    • B.E/B.Tech (EEE, ECE)
    ,

Keyskills :
board bringupcall of dutydevice modelingpower integritypcb designcadence allegrochanging the worldplatform design

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