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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Embedded / System Software,Embedded, VLSI |
| EmploymentType | Full-time |
IP Logic Design Engineer.Job DescriptionThe IPG IP Engineering Group is looking for energetic and passionate Front End Design Engineer. You will work on high-speed digital design targeted towards low power optimized IP implementations. Your responsibilities will include but are not limited to- setting up Automation flows for IP Logic Design , ensuring RTL quality by setting up and maintaining Front End tools like Lint, CDC, VCLP, Synthesis QA checks, GIT Repo etc , creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc.You will also have an opportunity to work on ensuring the RTL quality of IP is high and will contribute to automating various Front End Tool, Flows and Methods. You will be able to utilize your scripting skills to innovate the IP RTL delivery to Validation teams, Backend Teams as well as SoC teams.The ideal candidate should exhibit behavioral traits that indicate: Excellent written and verbal communication skills are critical on a small, fast-moving team. As part of a growing, dynamic new business, the candidate must be successful working with many cross functional teams and manage multiple tasks and changing requirements, in an innovative environment.QualificationsThe successful candidate will possess a BS, MS degree with a minimum of 2 years of relevant industry experience. Additional qualifications ideally include: Strong scripting skills, experience in working with Front End design tools, Synthesis, Low power design, understanding analog design concerns and driving to an optimal solution between analog and digital designs, familiarity with pre-silicon and post-silicon validation. Experience in the following areas/ skills are desired: Git/Perforce/CVS know how Perl/Python/TCL Spyglass Lint, CDC, DFT, VCLP, Logic design using System Verilog Low-power design using UPF and clock gating Multiple clock domain design State machine design Simulation and debug experience using VCS/Verdi Synthesis and speed path debugInside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.,
Keyskills :
controllingdiagnosticsfftgsmfront end designfront endnew businesslogic designanalog designmachine designsystem verilogdigital designcadencehighspeed digital designlowpower design