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Lead Design Engineer

2.00 to 5.00 Years   Bangalore   20 Sep, 2019
Cadence Design
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaEngineering Design / ConstructionR&D / Product Design
EmploymentTypeFull-time

Job Description

  • Responsibilities includes knowledge of Serdes IP design, lint, synthesis, static timing analysis, DFT, formal verification, at block, core, and chip levels.
  • Defining DFT architecture - # of Scan chains, clock domains and DFT wrapper for analog-digital boundaries, clock / reset bypassing etc.For both Testchip and IP versions.
  • Interact with PD team for Scan insertion and generating patterns to determine the Test and Fault coverage against the target goals as per Specifications
  • DC/AC and At-speed Scan, MBIST, JTAG and test logics at IP and Test chip level etc.
  • interfaces with PD team to analyze coverage for Pre- Scan and post-scan stitched netlist, analyze timing paths for Scan hold fixes and subsequent test vector generation for functional and scan.
,

Keyskills :
catiav5 autocad drawing welding bom statictiminganalysis scaninsertion timinganalysis malverification

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