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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | Web Design |
| EmploymentType | Full-time |
Lead Physical Design Engineer Job description Education :BTech in EC / EE / Telecommunication is must. MS / MTech VLSI is preferredNo. of positions :3APPLY Desired Skills: Minimum 4+ year of experience Should have block / SOC level netlist - gds2 experience. Expertise in Floorplaning , Power planning , CTS. Should be capable of handling block - level timing closure. Should have knowledge on all low powersignoff checks , like MVRC / CLP , LEC / Formality , DRC , LVS , IR , EM. Good scripting skills (TCL / SHELL). Experience on low power implementation techniques is preferred. Synopsys / Cadence tool experience is preferred. Should be capable to lead a team of 5+ junior engineers. Should be able to provide any training / guidance that team members need Bachelor degree in EC / EE is must or Mater degree in VLSI is preferred. Good communication skills. Interested candidates , please send your latest resume tohrsignoffsemi.com,
Keyskills :
vlsiplanningroutingverificationsocleccadencechecksclpresumeeducationdesigntiminglvstrainingdrcfloor planningphysical design