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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Physical DesignExperience: 4 to 8 YearsEducation: BE / ME / B. Tech / M. Tech in EEE/ ECE/ EI/ CSNo. Of Positions: 20+ (Including 2 Leads / 2 Experts) Location: BangaloreAbility to handle the complete physical design and analysis of multiple designs independently. Good understanding of the static timing analysis and experience of closing timing requirements on multiple designs. Experience of closing power analysis (IR/ EM) , equivalency checks as well as low power checks. Ability to run the physical verification as well as fix all the violations independently. Exposure to the challenges in the physical design of chips targeted to 28nm/ 16nm / 7nm technology. Experience in writing scripts using standard scripting languages (TCL/ Perl) . Good communication skills. 4 years of experience in physical design. The job will involve working on multiple block level designs to close all the implementation, timing, power, and physical verification-related issues. The candidate is also expected to contribute to the chip level analysis runs and solve some of the complex issues in the design.,
Keyskills :
static timing analysispower analysisphysical designtiming analysisphysical verificationdesigntimingcheckswritingscriptsanalysisscriptingcommunicationimplementationTiming ClosurePrimetimeClock Tree Synthesi