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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Responsibilities* Create verification test plans* Drive/Participate in discussions across various disciplines to get a clear understanding of requirements* Develop the architecture and design of the verification environment in OVM/UVM* Develop/run/debug tests in SystemVerilog* Mentor other engineers in using the verification infrastructure and creating test benches* Ownership of verification of block/cluster/ip/subsystem or chip level testing* Actively review code created by fellow team mates* Participate in func coverage, code coverage reviews and provide/implement feedback* Contribute to the development and maintenance of long term design verification strategy* Track progress of self/subteam to achieve goals timely* Provide indicators and guidance to management on issues and roadblocks on a timely basis* Be able to work with teams across geosRequirement:* Experience with creation of plans, schedules and cost estimates for design verification efforts* Experience in development and deployment of verification strategies and methodologies across teams and organizations* Apart from simulation, should have work experience with at least one other verification aspect like Performance modeling, Formal verification, Gate Level verification, Emulation, etc.* Experience with implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage* Proficiency in SystemVerilog* Hands on experience and significant expertise with OVM/UVM is a must* Proficiency in scripting languages and utilities including Make, Perl, Python, etc.* Expert level knowledge of simulation tools such as VCS from Synopsys* Very good knowledge of automation concepts and significant experience working with SCM/CI tools and infrastructure* Experience in network ASIC design verification is a plus with protocols such as Ethernet, Memory buses, PCI-Express, etc* Hands on Experience in C/C++ is highly desirable* Should be able to contribute as IC or technically leading a group of team for a Focus/CTE as per requirementQualificationsQualifications: Professional Knowledge: * 8-12 years of domain experience out of which 4+ years of hands-on verification experience using SystemVerilog and OVM/UVM * Strong understanding of engineering design principles * 4+ years of Experience and working knowledge of one or more of the following interfaces: DDR3/4, GbE, IDI, FSB, JTAG, I2C, SATA, SMBus, SPI, USB2/3. * 4+ years of experience working with and familiarity with PCIe. * Proven track record in ASIC verification from environment development to tests development * Excellent written and verbal communication skills,
Keyskills :
data centerasic designcode coverageasic verificationcommercial modelsengineering designbehavioral trainingformal verification