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| Job Location | Bangalore |
| Education | Not Mentioned |
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| EmploymentType | Full-time |
Experience:5+YrsLocation- BangaloreDesignation:Project LeadBudget: As per experience we can give decent hikeJD:Must have experience inEthernet 25G, 100G based5+ years of relevant experience in the FPGA domain.Worked on Xilinx / Altera FPGAsHave in depth knowledge of FIFO / Clock domain crossing / clock data recovery.Strong in VHDL / Verilog RTL coding.Strong in FPGA design synthesis & timing closure.Candidate from NITs / CDAC Pune / IIT preferred ,
Keyskills :
fpga designrtlfpgavhdlfifodesignalteratimingverilogsynthesisAlteraComplex Programmable Logic DeviceActelRTL DesignModelSimRTL CodingSynplify ProMicroblazexilinxXilinx