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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Rs 12 - 22 Lakh/Yr |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Design RTL-SOC-IP-STA-Synthesis Engineer ( Experience 2- 10 yrs )MULTIPLE Positions ranging from Junior to Lead Engineer. Sound experience in RTL Design is REQUIRED ranging from 2 to 8 Years. The open Design positions in different teams are:- 1.CPU Design (CPUSS)/ ASIC Design / SOC Design / GPU Design 2.Component Design / IP Design 3.Logic Design / Micro-Architecture 4.Synthesis/STA 5.Modem Design 6.Low-Power Design And many more. The selected candidate will have the following responsibilities: Block level RTL (Verilog or System Verilog) design from micro-architecture level specifications. Implementation of Low power logic, targeting power, performance, area, and timing goals. Linting, CDC, LEC and preferably Low Power check tools to implement design and check design quality Work with Design Verification team on block and top-level functional/gate level verification and code coverage, including Power aware debug. ,
Keyskills :
rtldesign asicdesign codecoverage designverification ip soc rtl lec cdc design timing performance gpu RTLCoding NCSim AMBAAHB TimingClosure Primetime RTLVerification sic