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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Rs 10 - 20 Lakh/Yr |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
STA Synthesis 2-10 yearsSTA & Synthesis Design 2-10 years Responsible for full chip level timing constraints (STA) , power aware physical synthesis and formal verification Formal verification for RTL-2-gates and gates-2-gates Physical Aware synthesis Expert in debugging STA timing constraints Handle conformal ECO generation independently. Power aware synthesis and physical aware synthesis. UPF 2.0 based power aware equivalence checking using Conformal. Debugging PA-FV failures Conformal ECO for doing complex functional ECOs. Low power synthesis on smaller blocks and subsystems using DC/Genus Perl/tcl scripting will a plus Keywords Synthesis, STA, SoC, Conformal, Timing Constriantsetc. ,
Keyskills :
physicalsynthesis formalverification equivalencechecking soc sta eco design timing scripting synthesis debugging PR EquivalenceChecking FirstEncounter ConformalLEC UPF ClockTreeSynthesis PowerAnalysis agma PlaceRoute