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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
2. Senior Member Technical Staff - SerDes Design and Verification Job Description The job function demands for the deep understanding on the protocols like USB, PCIE, MIPI, JEDEC, I2C, SPI etc. Design/ verify the RTL code for the high speed SerDes related digital blocksExcellent verbal and written communication skills are required. Experience in synthesis of complex SoCs block/ top level and writing timing constraints. Experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints. Experience in post-layout STA closure and timing ECOs Excellent problem solving and debug skills Worked in technology nodes 45nm and below. Knowledge of low-power aware implementation is a plus Mandatory Skills Timing Closure, STA, ECOs, Synthesis, SDCBE/ B. Tech in VLSI/ ECE. 5+ years of experience in verification of analog mixed signal blocks. Hands on tool expertiseTools: cadence AMS tools and proficiency in Verilog, verilogA and VAMS languages,
Keyskills :
javalinuxautomationjavascriptproblemsolvingcommunicationskillsspidftrtlstai2camsvlsiramewmixedsignalsignaltimingtimingclosuremalverificationwrittencommunicationusb