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SerDes Architect

6.00 to 10.00 Years   Bangalore   16 Aug, 2022
NXP Semiconductors
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryManufacturing
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

    The AMSIP team is part of NXPs Central Technology Organization (CTO). AMSIP employs about 80 specialists located in Eindhoven, Bangalore and Noida with strong focus and competence in developing state-of-the-art Data Converter, Reference and Power Management IPs that support all NXP Business Lines. AMSIP team specializes in architecting, designing, and delivering analog and mixed-signal building blocks that are at the heart of competitive NXP products.Continuing on its growth trajectory, fueled by decades of success stories and execution excellence, AMSIP is expanding into developing High Speed Serial Link (HSL) PHYs to support ever growing need of SERDES PHYs by NXPs Automotive and non-Automotive product lines.As the HSL architect you will be responsible for, but not limited to, defining technical roadmap, interacting with the end customers to gather requirements, translating them into product specifications and defining sub-system design architecture to meet performance, quality and cost targets in close coordination with AMSIP-HSL design team.As the HSL Architect you will be responsible for:Developing technical roadmap that are in sync with various NXP product line (PL) requirementsInteracting with various NXP PLs to gather their product requirements and translating them into SERDES PHY features and specificationsDeveloping serdes architectures to meet performance, quality, reliability and cost objectivesSerdes architecture development including equalizers and time recovery for NRZ and PAM4 systems.End to end system modeling, simulation and performance analysis including losses, crosstalk & jitterPerforming design trade-off analysis and provide implementation recommendations to circuit & RTL designersClose collaboration with silicon and package designers to satisfy signal/power integrity and EMI requirementsHands-on experience in silicon validation of PHY is a plusTechnical ownership of the overall PHY (TX/RX/Common Lanes/Digital) development and making sound decisions that address micro-architecture implementation challenges to meet performance, quality, reliability and cost.Develop and drive best design, layout, validation practices for the HSL team in adherence to standard NXP process and flowsCandidate ProfileTo be successful in this role you have:Masters or a PhD in Electronics and Communication Engineering15+ years of experience in Analog Mixed Signal Design that includes 5+ years of experience in multi-GHz High Speed transceiver Architecture and Circuit Design developmentGood system level understanding of communication and network interconnect protocols like PCIe, USB and Ethernet protocols in the context of PHY architecture, circuits and system design and developmentBroad exposure to CMOS and Bi-CMOS Mixed Signal SoC and HSL product development life cycle with several successful product releases to marketDeep expertise in in designing/modelling/optimizing SerDes blocks like Tx driver, channels, RX CTLE, Termination, DFE, Clocking for NRZ/PAM-4 SerDes PHY is a mustDeep expertise in high-speed transceiver Equalization and relevant Design Techniques to improve Bandwidth, Noise, Linearity, Jitter and CDR performanceExperience in leading multi-site, multi-disciplinary (Analog/Digital Design, Layout and Si validation) technical teamsExcellent communication, presentation and leadership skills.,

Keyskills :
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