SOC Design Engineer kdayj_7148

Job Description

Job ID: JRhidden_mobileJob Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSOC Design Engineer Job Description We are an end-to-end design team based in Bangalore part of Intel Labs. In this position, you will be responsible for the back-end design tasks and support design implementation and integration including Logic synthesis, Layout & Floor planning and full chip integration and timing roll-up. In this position, your responsibilities will include the following: - Working closely with the Design and Micro-Arch team in studying, understanding, analyzing the micro-arch specifications and own Partition/Block level, IP level layout. - Interacting with micro-architects and the design team in areas of Logic synthesis, Layout methodology development, and Performance/Layout verification to ensure that layout goals are met. - Participating in Partition and IP floor-planning and implementing the physical layout for the IP. - Verifying and ensuring that Area/Power/Performance specifications are met. - Ownership of synthesis in order to estimate power and timing constraints at IP, partition and full chip level - Own IP block level floor planning, APR and timing closures Qualifications Minimum QualificationsYou should possess a Masters degree in EE with at least 3 years of experience or a Bachelors degree in EE with at least 4 years of experience in VLSI physical design. Additional qualifications include: - Knowledge of microelectronics designs, semiconductor device physics, CMOS process and physical layout - Good hands-on Knowledge on EDA tools like Synopsys design tools in the field of logic and physical design.- Experience in STA, LEC-Formal verification, Redhawk IR-drop analysis and low power verification would be a plus.- Good knowledge in scripting languages specially in Perl/Python*, Tcl* and Shell (csh/tcsh/bash) scripting would be a plus.- Familiarity with hardware description language such as Verilog* or System Verilog* - Hands-on experience in converging complex blocks from RTL to GDSII (100K-1 million gates) with embedded black-boxes. - Strong background in converging power, timing and functional equivalence is required. - Exposure to handling APR blocks associated with Analog IPs like DDR and PCIe would be a plus- Experience in design automation for design methodology and flow development.Preferred Qualifications:-Firm grasp of programming tools and knowledge in VLSI domain-Excellent working ability with circuit design and layout methodologies in a team environment.-Capable of sharing tool knowledge and expertise with other physical designers and contribute to a positive team environment through developing and proliferating best known methods-Ownership, communication, and influencing skills.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Inside this Business Group Intel Labs is the companys world-class, industry leading research organization, responsible for driving Intels technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intels growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJRhidden_mobileBangaloreIntel Labs,

Keyskills :
drawingautocaddraftingmodelingcadhardware description languageeda toolsfloor planningcircuit designlogic synthesisbehavioral trainingsemiconductor device