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SoC Design Engineer - Scan Insertion/DFT Timing

2.00 to 5.00 Years   Bangalore   26 Apr, 2022
Intel Technology India Pvt Ltd
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaR&D / Product Design
EmploymentTypeFull-time

Job Description

    SoC Design Engineer - Scan Insertion/DFT Timing Job DescriptionStrong knowledge of DFT architectures and methodologies which includes Scan Architecture, Scan Insertion, ATPG, Generating Timing exceptions for Scan, Mbist, BScan, IO DFx, analog DFT, JTAG, Boundary scan etc. and DFT Design Rule checks for netlists. Proven knowledge of Verilog, System Verilog, RTL design and Digital Logic. Strong knowledge of SoC tools/methodology (VCS, Synthesis, Spyglass, Tessent, Primetime, Design Compiler, etc. ). In addition, this position requires interaction with the Frontend, Backend design teams, CAD teams and post-silicon/ATE teams. Strong automation and debug skills and hands-on experiences in Perl/Python and TCL scripting are a must.Qualifications Electronics Engineer with at least B.Tech 5yrs + or M.Tech with 2+ yrs experience in DFT, Scan Insertion, DFT Timing, Design Quality checks and related areas. o Knowledge in RTL design, Digital Logic, DFT features and Design quality checks o Experience in Scan Architecture, Scan Insertion, ATPG and Mentor Tessent tool is must o Expertise in automation, methodology development and scripting language like Perl/Python/Tcl in Unix environment o Self-Starter with strong multitasking skills Personal: o Good interpersonal communication skills with an ability to work in a team o Quick learner, proactive and self-motivated, eager to learn and contribute o A sense of ownership, commitment, and responsibility o Possesses strong analytical and communication skills o Has a growth mindset and is aligned with Intel valuesInside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore s Law and groundbreaking innovations. DEG is Intel s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJRhidden_mobileBangaloreDesign Engineering Group,

Keyskills :
drawingautocaddraftingmodelingcadcontinuous improvement facilitationfront endrtl designboundary scansystem verilogscan insertionbusiness unitsdesign compiler

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