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SoC Design Verification Engineer

5.00 to 9.00 Years   Bangalore   30 Mar, 2021
Intel Technology India Pvt Ltd
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaNetwork / System Administration
EmploymentTypeFull-time

Job Description

  • The candidate will work as a member of a verification team playing a key leading role in developing Ethernet Network Interface Controller products The responsibilities will include but not be limited to
  • Create review and signoff verification test plans
  • Drive, Participate in discussions across various disciplines to get a clear understanding of product features and its validation requirements
  • Develop the architecture and design of the verification environment in OVMUVM
  • Development of test plans test bench BFMs checkers monitors trackers scoreboard and functional coverage
  • Develop run debug tests in SystemVerilog Mentor other engineers in using the verification infrastructure and creating test benches
  • Ownership of verification of block cluster ip subsystem or chip level testing
  • Drive and participate in verification code func coverage RTL code coverage reviews and provide implement feedback across the project
  • Contribute to the development and maintenance of long term design verification strategy Track progress of self sub team to achieve goals timely
  • Provide indicators and guidance to management on issues and roadblocks on a timely basis
  • Be able to work with teams across geos
  • Should be able to contribute as IC or technically leading a group of team for a Focus CTE as per requirement
  • Develops preSilicon functional validation tests to verify system will meet design requirements
  • Creates test plans for RTL validation defining and running system simulation models and finding and implementing corrective measures for failing RTL tests
  • Analyzes and uses results to modify testing
Qualifications
  • BE/BTech or ME/MTech 7-9 years of domain experience out of which at least 5 years of hands-on verification experience using SV and OVMUVM
  • Proficiency in SV OVM UVM and object oriented programming
  • Strong understanding of engineering design principles
  • Proven track record in ASIC verification from environment development to tests development to validation closure
  • Excellent written and verbal communication skills Very good at creation of test plans schedules and cost estimates for design verification efforts
  • Experience in development and deployment of verification strategies and methodologies across teams and organizations
  • Apart from simulation should have work experience with at least one other verification aspect like
  • Performance modeling
  • Formal verification Gate Level verification Emulation etc
  • Very good knowledge of a vertical networking or connectivity technology or protocol Eg PCIE Ethernet Packet Processing RDMA Memory Controller etc
  • Proficiency in scripting languages and utilities including Make Perl Python etc
  • Expert level knowledge of simulation tools such as VCS from Synopsys Very good knowledge of automation concepts and significant experience working with SCMCI tools and infrastructure Experience in network ASIC design verification is a plus with protocols such as Ethernet Memory buses PCIExpress AMBA protocols RDMA etc Hands on Experience in CC is highly desirable
,

Keyskills :
verificationuvmdesignfailure analysisdata centerasic designcode coverageasic verificationsystem simulationengineering designbehavioral training

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