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Soc Design Verification Engineer

5.00 to 9.00 Years   Bangalore   07 Sep, 2021
Intel Technology India Pvt Ltd
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

Soc Design Verification EngineerJob DescriptionThe candidate will work as a member of a verification team, playing a key/leading role in developing Ethernet Network Interface Controller products. The responsibilities will include but not be limited to:

  • Create/contribute to verification test plans
  • Understand the architecture and design of the verification environment in OVM/UVM and create components used by test environment
  • Develop/run/debug tests and functional coverage in SystemVerilog
  • Ownership of verification of block/cluster level testing or a significant feature set in a chip/subsystem level testing
  • Participate in code review process and provide/implement feedback
  • Participate in func coverage, code coverage reviews and provide/implement feedback
  • Able to use automation and productivity tools to maximize impact on overall schedule
  • Track progress to achieve goals timely
  • Contribute to the development and maintenance of long term design verification strategy
  • Be able to work with teams across geos
Qualifications
  • BE/BTech or ME/MTech 7-9 years of domain experience out of which at least 5 years of hands-on verification experience using SV and OVMUVM
  • Proficiency in SV OVM UVM and object oriented programming
  • Strong understanding of engineering design principles
  • Proven track record in ASIC verification from environment development to tests development to validation closure
  • Excellent written and verbal communication skills
  • Very good at creation of test plans schedules and cost estimates for design verification efforts
  • Experience in development and deployment of verification strategies and methodologies across teams and organizations
  • Apart from simulation should have work experience with at least one other verification aspect like Performance modeling Formal verification Gate Level verification Emulation etc
  • Very good knowledge of a vertical networking or connectivity technology or protocol Eg PCIE Ethernet Packet Processing RDMA Memory Controller etc
  • Proficiency in scripting languages and utilities including Make Perl Python etc Expert level knowledge of simulation tools such as VCS from Synopsys Very good knowledge of automation concepts and significant experience working with SCMCI tools and infrastructure
  • Experience in network ASIC design verification is a plus with protocols such as Ethernet Memory buses PCIExpress AMBA protocols RDMA etc
  • Hands on Experience in CC is highly desirable ,
,

Keyskills :
verificationuvmdesignfailure analysisdata centerasic designcode reviewcode coverageasic verificationcommercial modelsproductivity tools

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