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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Cement / Building Material |
| Functional Area | TestingGeneral / Other Software |
| EmploymentType | Full-time |
Define and Implement the ASIC/ SoC/ IP verification environment using System Verilog and UVM. Support the development of verification test plans, test suites and verification activities. Develop support utilities for verification automation, test bench automation and regression to improve productivity and functional coverage. Required Skills: Good knowledge on SoC design architecture and must have completed verification of one or more embedded processor based SoC. Strong knowledge on SoC/ ASIC verification flow RTL, Gate level, and Low power verification. Proven experience of the design verification methodologies such as UVM, coverage driven verification (code & functional) and constraint random test generation techniques. Good protocol knowledge on PCI express (Gen3/ Gen2) is mandatory Must have good knowledge on PCI- ex (Gen3/ Gen2) IP/ SoC verification Good knowledge on C/ C++ and ARM processor is plus. Good verbal and written communication skills. ,
Keyskills :
verification uvm design failureanalysis ip testsuites systemverilog socverification asicverification designverification writtencommunication arm soc rtl pci asic verilog express rmprocess