Sr Member Technical Staff

Job Description

At Rambus, we are turning incredible possibilities into everyday reality by helping to deliver the innovations that greatly impact the world we live in. We create leading- edge semiconductor and IP products, spanning memory and interfaces to security to smart sensors. Our products are integrated into tens of billions of devices and systems around the globe, running critical applications for Big Data, Internet of Things (IoT), mobile, consumer and media platforms. And our history runs deep - we have been in Silicon Valley for 25 years and are continually anticipating key technology trends and are developing innovations that drive market changes. From a pure IP provider to becoming a fabless chipmaker, Rambus is evolving to address critical challenges in the semiconductor industry. As a dynamic organization, we are always seeking to hire exceptional talent to join some of the brightest inventors and engineers in the world to explore their passions to develop products that have real life impact. As well, Rambus benefits are among the most comprehensive and competitive in Silicon Valley. ResponsibilitiesDevelop micro- architecture and RTL design for digital components for serdes IPs and testchips Generating soft- macros (RTL) to be used in test- chip/ product designs Setup and analysis of lint, synthesis, timing closure and DFT reports Support Customer integration activities Be a technical digital design lead for the PHY IP s. Own the design and methodology for execution on multiple IP s on multiple technology nodes Define or participate in micro- architecture definition and drive for power, performance and area (PPA) targets/ enhancements QualificationsElectrical/ Electronic Engineering with at least 5 years of experience in Logic design, Micro architecture definition, RTL design and STA Experience working with multiple clock domains, high speed designs Experience with synthesis flow, hands on timing closure, ECO iterations Knowledge of serdes technology such as - PCI Express, Ethernet, USB is a plus Driving design flows and overall methodology. Experience in leading projects to deliver high- speed, high- performance IP design over advance technology nodes Experience in leading both IP design and TestChip/ SoC integration. Experience in the design of digital circuits and components in RTL, building/ own the top- level integration as well as in synthesis, timing closure, and power- optimization of digital designs. Experience coding within Verilog and/ or System Verilog along with scripting languages such as Perl, Tcl, or Python. Hands on experience on Lint/ CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed- signal simulation environment, etc. Experience in cross interaction with verification, DFT and physical design teams. Rambus offers a competitive compensation package, which includes a strong base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time- off program and gym membership. Rambus creates cutting- edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting. Our chips, customizable IP cores, architecture licenses, tools, services, training and innovations improve the competitive advantage of our customers. We collaborate with the industry, partnering with leading ASIC and SoC designers, foundries, IP developers, EDA companies and validation labs. Our products are integrated into tens of billions of devices and systems, powering and securing diverse applications, including Big Data, Internet of Things (IoT), mobile, consumer and media platforms. At Rambus, we are makers of better. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/ careers/ .,

Keyskills :
java cisco environment linux ompetitiveadvantage systemverilog projectadministration logicdesign physicaldesign internetofthings technologytrends bigdata digitaldesign