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Sr Physical Design / Synthesis / DFT Engineers ASICBangalore

2.00 to 5.00 Years   Bangalore   13 Apr, 2020
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryRecruitment Services
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

Sr Physical Design / Synthesis / DFT Engineers ASICBangalore Implementation of multimillion gate SoC designs in cutting edge process technologies (65nm, 40nm and 28nm)Work on all aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout,

Keyskills :
atpg dft scan silicon clocktreesynthesis planning timingclosure physicaldesign signalintegrity parasiticextraction physicalverification ir ip soc dfm edge ertms design timing flo

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