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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Recruitment Services |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Sr Physical Design / Synthesis / DFT Engineers ASICBangalore Implementation of multimillion gate SoC designs in cutting edge process technologies (65nm, 40nm and 28nm)Work on all aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout,
Keyskills :
atpg dft scan silicon clocktreesynthesis planning timingclosure physicaldesign signalintegrity parasiticextraction physicalverification ir ip soc dfm edge ertms design timing flo