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Sr Principal Design Engineer

7.00 to 10.00 Years   Bangalore   29 Nov, 2022
Cadence Design
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

    Key Qualifications:Expertise in logic synthesis, conformal, static timing analysis, custom clock tree development and Place and Route (PnR)Hands on experience in all aspects of the chip development processDeep understanding of technology files, QRC files, library characterization and technology marginsExperience in creating or improving low power synthesis methodologiesExperience with scripting languages like Perl, Tcl or PythonFloorplan, Place and Route at block level, physical design verification, LVS, DRC, IR drop analysis; netlist to gds at block levelRTL logic design or implementation experience on multi-million gate ASICs will be a plusStrong communication skills to effectively communicate across all internal groupsDescription:As a synthesis, PnR Engineer, you will have responsibilities spanning various aspects of SOC design and implementation. Responsible for activities like Synthesis, clock tree synthesis, custom clock tree, P&R etc. You will be working closely on methodology for improving synthesis QOR. Responsible for floor planning, placement and routing at block level. Will need to work closely with other engineers that are members of the RTL, STA and Physical Design teams.Education & Experience:BS or MS in EE, EECS, or CS is required4+ years relevant work experience,

Keyskills :
lightingestimation3d modellingahu

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