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Silicon AI/ML DFT Engineer, TPU, Google Cloud

3.00 to 6.00 Years   Bengaluru/ Bangalore (Karnataka)   21 Mar, 2025
Google India Pvt Ltd
Job LocationBengaluru/ Bangalore (Karnataka)
EducationML/ LLM (Law)Any Graduate
SalaryAs per Industry Standards
IndustryInternet/Dot com/ISP
Functional AreaProduction/Manufacturing/Maintenance/Packaging
EmploymentTypeFull-time

Job Description

Silicon AI/ML DFT Engineer, TPU, Google CloudLocation: Bengaluru, Karnataka, IndiaExperience Level: MidMinimum qualifications:

  • Bachelors degree in Electrical Engineering or a related field, or equivalent practical experience.
  • 3 years of experience in DFT specification definition, architecture, and insertion.
  • Experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent).
  • Experience with ASIC DFT synthesis, STA, simulation, and verification flow.
Preferred qualifications:
  • Masters degree in Electrical Engineering.
  • Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST).
  • Experience in SoC cycles, including silicon bring-up and silicon debug activities.
  • Experience in fault modeling.
  • Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
About the jobIn this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Googles most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles TPU. Youll contribute to the innovation behind products loved by millions worldwide and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.You will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for next-generation SoCs while working with the DFT Organization. You will design, insert, and verify the DFT logic and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Googles product portfolio possible. Were proud to be our engineers engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities
  • Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO.
  • Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks.
  • Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
  • Document DFT architecture and test sequences, including boot-up sequence associated with test pins.
  • Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve test quality and support post-silicon test team.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Googles Applicant and Candidate Privacy Policy.Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Googles EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Keyskills :
dft methodologies asic design flow eda tool proficiency silicon debugging test strategy development production action alias innovation test equipment cutting compression

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