Senior Design Verification Engineer

Job Description

As a Design Verification Engineer, you will be responsible for verifying digital designs using SystemVerilog / UVM and ensuring the functionality of ASIC/SoC. Your key responsibilities will include:- Strong experience in SystemVerilog / UVM- Experience in ASIC/SoC Verification- Knowledge of verification methodologies- Experience in testbench development- Debugging and verification of digital designs- Good understanding of protocols like PCIe / AXI / AMBA (preferred)To qualify for this role, you should hold a B.E / B.Tech in Electronics & Communication Engineering / Electrical Engineering.If you are interested in this position, please share your CV to the provided email address. As a Design Verification Engineer, you will be responsible for verifying digital designs using SystemVerilog / UVM and ensuring the functionality of ASIC/SoC. Your key responsibilities will include:- Strong experience in SystemVerilog / UVM- Experience in ASIC/SoC Verification- Knowledge of verification methodologies- Experience in testbench development- Debugging and verification of digital designs- Good understanding of protocols like PCIe / AXI / AMBA (preferred)To qualify for this role, you should hold a B.E / B.Tech in Electronics & Communication Engineering / Electrical Engineering.If you are interested in this position, please share your CV to the provided email address.

Keyskills :
SystemVerilogUVMDebuggingPCIeAXIAMBAASICSoC VerificationVerification methodologiesTestbench development