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Engineer II Verification Job in Statewide , Tamil Nadu for Microchip Technology Inc. | Technical Job Description To play the role of verification engineer at the Block level , chip level Functional ...
eda toolstest casescode coveragesystem verilogedasocrtluvmglsvcsovmvmmahbpcietamilncsimdesignwritingverilogusb30Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen4/Gen5, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CC...
javalinuxenvironmentsystem verilogelectrical engineeringrtluvmusbbusvmmaessatapcielessflashciscomentor graphicsipsSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingTo develop advanced High Speed Serial Links PHY s like DP/HDMI/USB3.0/SGMII and associated blocks like linear Regulators, Calibration , POR and Low Power Analog Major responsibilities include Develo...
linear regulatorsphydesigntestingplanningmentoringengineersleadershipinnovationcalibrationperformancedocumentationimplementationspecificationsBandgap ReferencesComparatorsLDOOpampCompany Profile: Western Digital Corporation is the world s largest data storage company with a leading portfolio of HGST, SanDisk, G-Technology and WD brands covering flash and disk-based ...
drawingautocaddraftingmodelingcadequal employment opportunitysystem designproduct designleadership skillsproduct developmentAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities : Design and lead high speed IP (USB3, PC...
rtl designdrawingautocaddraftingmodelinganalog designdigital designcommunication skillsphypciedesignsiliconinterfacesdocumentationcommunicationcadenceEngineer II Verification Job in Statewide , Tamil Nadu for Microchip Technology Inc. | Technical Job Description To play the role of verification engineer at the Block level , chip level Functional ...
eda toolstest casescode coveragesystem verilogedasocrtluvmglsvcsovmvmmahbpcietamilncsimdesignwritingverilogusb30Skill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingEngineer II Verification Job in Statewide , Tamil Nadu for Microchip Technology Inc. | Technical Job Description To play the role of verification engineer at the Block level , chip level Functional ...
eda toolstest casescode coveragesystem verilogedasocrtluvmglsvcsovmvmmahbpcietamilncsimdesignwritingverilogusb30Engineer II Verification Job in Statewide , Tamil Nadu for Microchip Technology Inc. | Technical Job Description To play the role of verification engineer at the Block level , chip level Functional ...
eda toolstest casescode coveragesystem verilogedasocrtluvmglsvcsovmvmmahbpcietamilncsimdesignwritingverilogusb30Worked on SOC level test bench and verification environment Testbench architecture, coding and good understanding of design issues in RTL Test bench generation, test vector creation, simulations, ga...
computer programmingsystem verilogarchitecturesimulationsocuvmverilogovmvmmedaAt Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Skill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexingSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layerchannel codingchannel estimationinterference cancellationestimationequalizationmultiplexing
Worked on SOC level test bench and verification environment Testbench architecture, coding and good understanding of design issues in RTL Test bench generation, test vector creation, simulations, ga...
computer programmingsystem verilogarchitecturesimulationsocuvmverilogovmvmmedaEngineer II Verification Job in Statewide , Tamil Nadu for Microchip Technology Inc. | Technical Job Description To play the role of verification engineer at the Block level , chip level Functional ...
eda toolstest casescode coveragesystem verilogedasocrtluvmglsvcsovmvmmahbpcietamilncsimdesignwritingverilogusb30Skill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleNvidia Silicon Solutions team is seeking world class Engineer to lead cross functional post-silicon development and validation of high speed SERDES on our state-of-the-art GPUs and SOCs. You will be p...
continuous improvement facilitationboard design logic designglobal teams circuit designsignal integrity equipment supplyfunctionTo develop advanced High Speed Serial Links PHY s like DP/HDMI/USB3.0/SGMII and associated blocks like linear Regulators, Calibration , POR and Low Power Analog Major responsibilities include Develo...
linear regulatorsphy designtesting planningmentoring engineersleadership innovationcalTo develop advanced High Speed Serial Links PHY s like DP/HDMI/USB3.0/SGMII and associated blocks like linear Regulators, Calibration , POR and Low Power Analog Major responsibilities include Develo...
linear regulatorsdesign testingAudio Amplifiers
Rtl Front end design engineer RTL frontend design Engineer 4- 6 years experience in Verilog / System Verilog RTL design and verification RTL synthesis using Design compiler FPGA Flow using Xilinx DFT ...
drafting drawing modeling cad spi arm autocad tldesign designcompiler frontenddesign systemverilog frontend hisSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultipleSkill Set: PCIe / Ethernet 1G / USB3.0 Experience : 4 - 8 Years UVM and Sytem Verilog is an must skill Must have develiped UVM based environment from scratch Shall have worked on PHY verifi...
open verification methodologymac layer channel codingchannel estimation interference cancellationestimation equalizationmultiple
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