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Analyst

8.00 to 12.00 Years   Mysore   22 Sep, 2024
Proxelera
Job LocationMysore
EducationNot Mentioned
SalaryNot Disclosed
IndustryEngineering / Construction
Functional AreaNot Mentioned
EmploymentTypeFull-time

Job Description

    Should have at least 8 years of experience in RTL design/integration, synthesis and static timing analysisShould have a good knowledge of industry leading synthesis and STA tools. Should have prior working experience at both IP and full-chip levels and should have supported in tape-out activitiesShould have experience in pre-layout and post-layout timing analysis and should have experience in working closely with physical design teams to achieve timing closureShould have good scripting abilities (PERL/TCL) and should have experience in setting up synthesis and STA flows from scratch,

Keyskills :
RTL designintegrationsynthesisstatic timing analysisPERLindustry leading synthesisSTA toolsfullchip levelstapeout activitiesprelayout timing analysispostlayout timing analysisphysical design teamsscripting abilitiesTCLsetting up synthesis

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