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Job Location | Delhi |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | BPO / Call Center |
Functional Area | Engineering Design / ConstructionGeneral / Other Software |
EmploymentType | Full-time |
Worked on SoC level testbench and verification environmentTestbench architecture, coding and good understanding of design issues in RTLTestbench generation, testvector creation, simulations, gate level simulationsHands on with System Verilog and Assertion based verification methodology Atleast 2years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM) Knowledge of RTL coding styles Low power verification (UPF/ CPF) would be an added plusExperience on System C would be an added plusWorked on protocols like AMBA AHB/ AXI, MIPI, PCI Express, SATA, USBEducationBE/ B.Tech./ MS/ M.Tech. (Electronics or Electronics & Communication),
Keyskills :
drawingautocad draftingmodeling cadassertion based verification rtl codingsystem verilog