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Job Location | Delhi |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | BPO / Call Center |
Functional Area | Engineering Design / Construction,R&D / Product Design |
EmploymentType | Full-time |
Worked on SoC level testbench and verification environmentTestbench architecture, coding and good understanding of design issues in RTLTestbench generation, testvector creation, simulations, gate level simulationsHands on with System Verilog and Assertion based verification methodology Atleast 4years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM) Should be able to work independently and able to guide other team membersProblem solving capabilities with leadership qualitiesShould have managed a team of 10 or more engineersSimulation Tools: NCSIM/ VCS/ ModelSim/ QuestaAdded Advantage: Knowledge of RTL coding styles Low power verification (UPF/ CPF) would be an added plusExperience on System C would be an added plusWorked on protocols like AMBA AHB/ AXI, MIPI, PCI Express, SATA, USBEducationBE/ B.Tech./ MS/ M.Tech. (Electronics or Electronics & Communication),
Keyskills :
graphic designcadmechanicalsalestenderassertion based verificationrtl codingsystem verilogproblem solvingsocrtlpciovmvmmaxihvlsataveraamba