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Lead Verification Engineer

3.00 to 7.00 Years   Delhi   28 Feb, 2022
Job LocationDelhi
EducationNot Mentioned
SalaryNot Disclosed
IndustryBPO / Call Center
Functional AreaGeneral / Other SoftwareEngineering Design / Construction
EmploymentTypeFull-time

Job Description

    Scan insertion and DRC cleanup Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading.Memory testing. Should also know the algorithms. Should also have knowledge about diagnostics. JTAG or P1500 or other interface mechanismDesirable competencies The candidate is expected to have exposure to :Compression tools is highly desirable LBIST, mixed-signal testing, logic equivalence Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required. Bridge fault detection is desirable ATE experience is an added advantageEducationBE/ B-Tech (Electronics/ Electrical/ Electronics &Comm) or MSc (VLSI/ Electronics/ Electrical/ Electronics &Comm) or MS or MTech would be preferred,

Keyskills :
verificationuvmdesignfailure analysisscan insertiondftrtldrcjtagscanbridgetestingwritingpatternelectronicscompressionFastscanDFT Compiler

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